In a process of manufacturing an electronic device, a mask is formed on a processing target layer, and an etching is performed to transfer the pattern of the mask on the processing target layer. As for the etching, a plasma etching may be used. A resist mask used for the plasma etching is formed by a photolithography technique. Accordingly, the critical dimension of the pattern formed on the processing target layer depends on the resolution of the resist mask formed by the photolithography technique. The resolution of the resist mask has a resolution limit. A demand for the high integration of an electronic device has increased, and it has been required to form a pattern having a dimension smaller than the resolution limit of the resist mask. Thus, as disclosed in Japanese Laid-Open Patent Publication No. 2004-080033, a technique has been suggested which adjusts the dimensional shape of the resist mask to reduce the width of an opening provided by the resist mask.